1. Field of the Invention
The present invention relates to a method and an apparatus for analyzing the operation of a microprocessor. The method according to the present invention is used for analyzing the program and operation of an instrument or apparatus in which a microprocessor is used and for inspecting a failure in operation of such instrument or apparatus, in the form of, for example, a microprocessor analyzer or an in-circuit emulator.
2. Description of the Prior Art
In general, in a system for the analysis of the operation of a microprocessor, the signals on the data, address, and control buses connected to the microprocessor are compared with predetermined reference conditions in a trigger comparison circuit, and a coincidence signal, i.e., a trigger signal, is generated when the states of the signals on the data, address, and control buses coincide with the predetermined reference conditions.
Meanwhile, a write signal for a trace memory and a clock signal for an address counter of the trace memory are generated in a control circuit in accordance with the signal on the control bus connected to the microprocessor. Upon receipt of a start signal, the prohibition of the delivery of the write signal for the trace memory and the clock signal for the address counter for the trace memory is released in the control circuit, and hence the control circuit causes the trace memory to store sucessively the states of the signals on the data, address, and control buses connected to the microprocessor.
When a trigger signal is generated, the delivery of the write signal for the trace memory and the clock signal for the address counter for the trace memory is again prohibited, so that the trace memory maintains the storage of the states of the signals on the data, address, and control buses connected to the microprocessor prior to the delivery of the trigger signal.
The stored states of signals on the data, address, and control buses in the trace memory are then converted into a hexadecimal code or a mnemonic code of the microprocessor, and the converted states of the signals are displayed on a display device, such as a cathode ray tube. Thus, it is possible to observe the sequence of the instruction execution by the microprocessor by the time the trigger signal is generated, and hence to discover errors in the used program and to carry out an analysis of the operation of the microprocessor.
In the above-described processes, the states of the signals on the buses are successively stored, in the trace memory in such a manner that all states of the signals on the buses, including interrupt routine and subroutine processes, are stored. However, where the discovery of the program errors and the analysis of the microprocessor operation is intended to be carried out under the condition that the interrupt routine and subroutine processes have been proved correct, it is not always necessary to store the correct processes of the interrupt routine and subroutine in the trace memory.
In this case, the storing of all states of the signals on the buses, including interrupt routine and subroutine processes, presents the undesirable effect wherein the analysis of the microprocessor operation cannot be effectively made. Even if the analysis of the main routine of the microprocessor is desired, most of the trace memory capacity is occupied by the storage of the interrupt routine and subroutine processes, and as a result, the utilization efficiency of the trace memory is deteriorated from the viewpoint of the analysis of the main routine. Thus, the above-described situation constitutes a problem in the prior art.
Also, it has been known in a prior art case that it has become necessary to trace the changes of the stack pointer in a stack memory in the microprocessor or in the system to be tested in order to analyze the program and operation of the microprocessor or to inspect failures of the operation. Errors in the program or failures in the operation often can be inspected by tracing the change of the stack pointer, particularly where the reason for the runaway of the program execution must be determined. In this case, each of the points where the stack pointer is changed must be determined and the analysis concerning the determined point must be carried out, since the entire program execution is successively stored in the trace memory. Since the capacity of the trace memory for storing the state of the signals on the buses is naturally limited, it is not desirable to attempt to increase that capacity. Thus, the above-described situation also constitutes another problem in the prior art.